Modern Front-end Support in gem5 [abstract]
Bhargav Reddy Godala, Nayana Prasad Nagendra, Ishita Chaturvedi, Simone Campanoni, and David I. August
ISCA 2023: The gem5 Workshop, June 2023.

Modern processors employ deep out-of-order pipelines to get more ILP and thereby improve IPC. Datacenter workloads suffer from Instruction supply problem to keep the backend of the CPU busy. Modern CPUs employ fetch directed instruction prefetching technique where the front-end of the processor runs ahead and warms up the instruction cache and fills prefetch buffers in the predicted path using Branch predictors. This method is commercially known as decoupled frontend or FDIP. Although modern decoupled front-ends have been around for over a decade but not seen in any well-known execution-driven simulators. In this talk, we will present an aggressive decoupled frontend model that we implemented in gem5 and various design changes made to the fetch and branch prediction units. We show performance improvement on widely used datacenter workloads from DaCapo, Renaissance, Cloudsuite v4, OLTP bench, Speedometer 2.0 suites, and spec workloads. We support FDIP for ARM as well as X86 ISA model in the gem5.