Abstractions in VHDL

This page discusses details of the VHDL language and the abstraction and modeling mechanisms presented here.

Note that VHDL is designed as an RTL level design language, not as a high-level modeling system. However, given that the system is structural and can be used for structural modeling, a comparison is useful.

Flexible Model Of Concurrency

VHDL uses a discrete event system to model time and deal with concurrency, and so is very flexible.

Optimizable/Analyzable Model of Concurrency

VHDL uses a discrete event model. The discrete event model is very general, but as a result, difficult to analyze. In general data may never even converge to a stable value in a cycle. Executable models built from VHDL descriptions are notoriously slow.

Data Abstraction

VHDL does support abstract data types, however, users must define all of the semantics regarding these types and thus they are difficult to use. Most users revert to using the IEEE standard types which are bit based, like Verilog.

Component Polymorphism

Data types on component ports must be specified when the component is designed, so there is no polymorphism.

Component Computation Customization

No mechanism for inheritance or higher-order functions is provided so the computation performed by components cannot be customized without altering the original component.

Control Abstraction

VHDL makes no attempt to abstract control or operation sequencing. All control is implemented explicitly.

Parametric Scalability

VHDL does not support parametric scalability since the sizes of data types and port arrays are fixed at component specification time.

Parametric Composition

VHDL does support a limited form of parametric composition, but only for regular structures through a parameterized interface.

Data Collection Abstraction

VHDL supports seperable data collection to some extent because the interpreted execution environments often allow probes to be inserted and state monitored. Unfortunatly, the actual mechansims for data collection outside the language in these tools is often primitive and thus they are cumbersome and difficult to use for sophisticated statistics collection.

Compile-time Knowledge of Structure

VHDL has a two-phase compilation scheme that resolves generators in the first phase and then compiles the model in the second phase, thus structure is known at compile time. Unfortunately, this compilation strategy does not allow high-level structure to be used to infer lower-level structure as happens in LSE.