Data Abstraction

At the high-level, the specific bit pattern used to represent data is not relevant and can requiring a particular bit encoding for data limits reusability of components. Data abstraction is simply using high-level data types that abstract the underlying representation to represent data in the system.

Data Abstraction is a relatively obvious concept and built in to most high level languages. However, when extending a low-level RTL language such as VHDL and Verilog to behavioral systems such as System Verilog, high-level data types must be added (as with Verilog) or the commonly used types modified to support data abstraction or replaced with types that support data abstraction (as with VHDL).

A summary of structural modeling systems and their support for data abstraction is presented here.

Synergies and Interactions

In the absence of Polymorphism and Component Computation Customization, high-level data types and data abstraction are fundamental. With polymorphism and computation customization, components can be built that respect data type given any bit representation. However, building components in this fashion would be incredibly tedious, and thus any reasonable high-level modeling system should support data abstraction.

The particulars of the type system itself, such as subtyping, can affect aspects related to Polymorphism(i.e. type inference).