Abstractions in Verilog
Note that Verilog is designed as an RTL level design language, not as a high-level modeling system. However, given that the system is structural and can be used for structural modeling, a comparison is useful.
Verilog uses a discrete event system to model time and deal with concurrency, and so is very flexible.
Verilog uses a discrete event model. The discrete event model is very general, but as a result, difficult to analyze. In general data may never even converge to a stable value in a cycle. Executable models built from verilog descriptions are notoriously slow.
All datatypes in Verilog are at the bit level so users must always specify the bit representation of data. Thus, there is no real abstraction of data.
Data types on component ports must be specified when the component is designed, so there is no polymorphism.
No mechanism for inheritance or higher-order functions is provided so the computation performed by components cannot be customized without altering the original component.
Verilog makes no attempt to abstract control or operation sequencing. All control is implemented explicity.
Verilog does not support parametric scalability since the sizes of data types and port arrays are fixed at component specification time.
Verilog does not support parametric composition since the structure of composite components are fixed at component specification time.
Verilog supports seperable data collection to some extent because the interpreted execution environments often allow probes to be inserted and state monitored. Unfortunatly, the actual mechansims for data collection outside the language in these tools is often primitive and thus they are cumbersome and difficult to use for sophisticated statistics collection.
Verilog does not support full algorithmic specification of structure and thus the structure is completely knowable at compile-time.