Hardware MultiThreaded Transactions [abstract] (ACM DL, PDF)
Jordan Fix, Nayana P. Nagendra, Sotiris Apostolakis, Hansen Zhang, Sophie Qiu, and David I. August
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2018.
Speculation with transactional memory systems helps programmers and compilers
produce profitable thread-level parallel programs. Prior work shows that
supporting transactions that can span multiple threads, rather than requiring
transactions be contained within a single thread, enables new types of
speculative parallelization techniques for both programmers and parallelizing
compilers. Unfortunately, software support for multi-threaded transactions
(MTXs) comes with significant additional inter-thread communication overhead for
speculation validation. This overhead can make otherwise good parallelization
unprofitable for programs with sizeable read and write sets. Some programs using
these prior software MTXs overcame this problem through significant efforts by
expert programmers to minimize these sets and optimize communication,
capabilities which compiler technology has been unable to equivalently
achieve. Instead, this paper makes speculative parallelization less laborious
and more feasible through low-overhead speculation validation, presenting the
first complete design, implementation, and evaluation of hardware MTXs. Even
with maximal speculation validation of every load and store inside transactions
of tens to hundreds of millions of instructions, profitable parallelization of
complex programs can be achieved. Across 8 benchmarks, this system achieves a
geomean speedup of 99% over sequential execution on a multicore machine with 4
cores.