Method and Apparatus for Enhancing Instruction Level Parallelism [abstract]
Wen-mei W. Hwu, Daniel A. Connors, David I. August, and John W. Sias
United States Patent Number 6,640,315, October 2003.

Disclosed is a method and system for handling inline recovery from speculatively executed instructions. Each register may be provided with an E-tag, that, when set, indicates an exception occurred in the generation of the value stored in its register, and an R-tag, which is used to manage data flow dependencies in recovery mode. Recovery is performed by re-executing speculatively those set of speculative instructions that are data flow dependent upon a first excepting speculative instruction. The disclosed invention provides an architecture and method for efficient exception handling when combining control speculation, data speculation and predication, thereby resulting in substantially enhanced instruction level parallelism.