Enabling Efficient Alias Speculation [abstract] (PDF)
Soumyadeep Ghosh, Yongjun Park, and Arun Raman
(LCTES), June 2015.
Microprocessors designed using HW/SW codesign principles, such as Transmeta
Efficeon and the soon-to-ship NVIDIA 64-bit Tegra K1, use dynamic binary
optimization to extract instruction-level parallelism. Many code optimizations
are made significantly more effective through the use of alias speculation. The
state-of-the-art alias speculation system, SMARQ, provides 40% speedup on
average over a system with no alias speculation. This performance, however,
comes at the cost of introducing new alias registers and increased power
consumption due to new checks for validating speculation. Consequently,
improving the efficiency of alias speculation by reducing alias register
requirements and rationalizing speculation validation checks is critical for the
viability of SMARQ. This paper presents alias coalescing, a novel technique to
significantly improve the efficiency of SMARQ through a synergistic combination
of compiler and microarchitectural techniques. By using a more compact encoding
for memory access ranges for memory instructions, alias coalescing
simultaneously reduces the alias register pressure in SMARQ by a geomean of
26.09% and 39.96%, and the dynamic alias checks by 20.73% and 33.87%, across the
entire SPEC CINT2006 and SPEC CFP2006 suites respectively.