Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures [abstract] (ACM DL)
Taewook Oh, Bernhard Egger, Hyunchul Park, and Scott A. Mahlke
Proceedings of the 2009 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2009.
In high-end embedded systems, coarse-grained reconfigurable architectures (CGRA)
continue to replace traditional ASIC designs. CGRAs offer high performance at a
low power consumption, yet provide flexibility through programmability. In this
paper we introduce a recurrence cycle-aware scheduling technique for CGRAs. Our
modulo scheduler groups operations belonging to a recurrence cycle into a
clustered node and then computes a scheduling order for those clustered nodes.
Deadlocks that arise when two or more recurrence cycles depend on each other are
resolved by using heuristics that favor recurrence cycles with long recurrence
delays. While with previous work one had to sacrifice either a fast compilation
speed in order to get good quality results, or vice versa, this is not necessary
anymore with the proposed recurrence cycle-aware scheduling technique. We have
implemented the proposed method into our in-house CGRA chip and compiler
solution and show that the technique achieves better quality schedules than
schedulers based on simulated annealing at a 170-fold speed increase.