Compiler Technology for Future Microprocessors [abstract] (IEEE Xplore, PDF, PostScript)
Wen-mei W. Hwu, Richard E. Hank, David M. Gallagher, Scott A. Mahlke, Daniel M. Lavery, Grant E. Haab, John C. Gyllenhaal, and David I. August
Proceedings of the IEEE, Volume 83, Number 12, December 1995.
Advances in hardware technology have made it possible for
microprocessors to execute a large number of instructions concurrently
(i.e., in parallel). These microprocessors take advantage of the
opportunity to execute instructions in parallel to increase the
execution speed of a program. As in other forms of parallel
processing, the performance of these microprocessors can vary greatly
depending on the quality of the software. In particular, the quality
of compilers can make an order of magnitude difference in performance.
This paper presents a new generation of compiler technology that has
emerged to deliver the large amount of instruction-level- parallelism
that is already required by some current state-of-the-art
microprocessors and will be required by more future
microprocessors. We introduce critical components of the technology
which deal with difficult problems that are encountered when compiling
programs for a high degree of instruction-level parallelism. We
present examples to illustrate the functional requirements of these
components. To provide more insight into the challenges involved, we
present in-depth case studies on predicated compilation and
maintenance of dependence information, two of the components that are
largely missing from most current commercial compilers.