ASPLOS XI Tutorial Call for Participation:
Using the Liberty Simulation Environment
with emphasis on validated OS-level simulation
Sunday, October 10, 2004
Boston, Massachusetts
The Liberty Simulation Environment (LSE) is a concurrent structural modeling tool that supports a new modeling methodology via a new hardware description language. The system allows designers and researchers to use a library of components to rapidly construct high-level models of hardware such as processors, ethernet controllers, and on-chip networks.
Participants will get a first-hand look at the latest LSE technology. We will describe the LSE methodology and the system itself, including the simulator builder and the model visualizer. Sample LSE models ranging in complexity from a simple DLX to a validated Itanium II machine model will be presented. Furthermore, participants will see how LSE can be used for OS research. Attendees will also get first access to the next LSE release.
Answers to Common Questions:Why would I want to learn LSE?- Because LSE allows very rapid construction of accurate simulators allowing you to focus more of your time and effort on ideas, not simulator construction. Highlights include a Princeton University built model of Intel's Itanium 2 whose CPI predictions are accurate to within 3%. This model was built by a single student in 11 weeks. Researchers at Rice University have built a remarkably accurate TIGON-2 Gigabit ethernet controller [Willmann '04 LCTES]. This model was built by 2 students in 6 weeks. (See the figures on the right.) Can I do this with C/C++?-Possibly, but writing a simulator in a purely sequential language such as C or C++ is extremely time consuming and error prone. This is because C/C++ does not provide the right kind of encapsulation for the computation in the hardware. We manage the complexity of hardware by dividing it into interconnected, concurrently executing hardware blocks and then reasoning about the blocks and their interconnections. This partitioning is not possible in a sequential language. Instead, they require an unnatural mapping of the hardware structure to a sequential simulator [Vachharajani '02 MICRO-35]. Simulators written in C are also difficult to understand. We asked users 10 questions about similar microarchitectures modeled using C and LSE. On average, users answered questions about the LSE model correctly more often than they did for the C model (see graph at right). More on this study can be found in this technical report.
Where can I find out more about LSE?- More
information on LSE and the techniques it uses to for rapid modeling
can be found on the web and in publications at MICRO-35, DAC 40, PLDI
2004, CODES+ISSS 2004, and LCTES 2004. See: Who is responsible for this?- Tutorial Organizer:David August, Princeton University ( august at cs.princeton.edu ) Contributors:
Manish Vachharajani, Princeton University |
Itanium 2 Model Predictions vs. Hardware 3COM TIGON-2 NIC Model vs. Hardware  Graph Showing Correctly Answered Questions  |